The field of the invention relates to memory devices and more particularly to non-volatile semiconductor memories.
The use of memory has been increasing due to rapid growth of storage needs in the information and entertainment fields and due to the decreasing size and cost of memory. One type of memory widely used is non-volatile semiconductor memory which retains its stored information even when power is removed. There are a wide variety of non-volatile memories. A typical commercial form of non-volatile memory utilizes one or more arrays of transistor cells, each cell capable of non-volatile storage of one or more bits of data.
Unlike random access memory (RAM), which is also solid-state memory, non-volatile memory retains its stored data even after power is removed. The ability to retain data without a constant source of power makes non-volatile memory well adapted for consumer devices. Such memories are well adapted to small, portable devices because they are typically relatively small, have low power consumption, high speed and are relatively immune to the operating environment.
In general, the small size, low power consumption, high speed and immunity to environment is derived from the structure of the memory. In this regard, such non-volatile memory devices are typically fabricated on silicon substrates. In addition, to obtain the advantages of small size, etc., and well as reduce costs, there is a continual effort to fabricate more circuitry within a given area.
For nonvolatile memory, a highly effective approach to increase density is to build monolithic three dimensional memories above the substrate, like those disclosed in Johnson et al., U.S. Pat. No. 6,034,882; Johnson et al. U.S. Pat. No. 6,525,953; Knall et al., U.S. Pat. No. 6,420,215; and Vyvoda et al., U.S. Pat. No. 6952043, all hereby incorporated by reference in their entirety.
The fabrication of these high density, three dimensional memory arrays presents a number of challenges. This includes misalignment of features during fabrication which results in reduced yield and which becomes more problematic as feature size is reduced. For example, where the photomask is improperly placed, the memory element may be short circuited during subsequent fabrication operations, or necessary electrical connections may fail to be made. Thus, alternate methods of fabrication are needed that reduce the difficulties of aligning memory elements during fabrication while permitting improved density, decreased future size, and improved yield.